 Semiconductor device
专利摘要:
PURPOSE: A semiconductor device is provided to prevent voltage drop of the inside of a semiconductor device while manufacturing the semiconductor device with smaller costs. CONSTITUTION: A semiconductor device is comprised of the first semiconductor chip where a semiconductor element is formed, the first connecting terminal arranged on a semiconductor element formation surface side in the first semiconductor chip and connected electrically to the semiconductor element, a conductive member buried in a through hole that goes through the first semiconductor chip, the second connecting terminal arranged on a back surface side of the semiconductor element formation surface in the first semiconductor chip, and connected electrically to the semiconductor element via the conductive member, a wiring substrate to which the first semiconductor chip is mounted, and the third connecting terminal at least portion of which is formed at a position corresponding to one of the first connecting terminal and the second connecting terminal, and which is electrically connected to the one of the first connecting terminal and the second connecting terminal. 公开号:KR20020028812A 申请号:KR1020010062109 申请日:2001-10-09 公开日:2002-04-17 发明作者:스기자끼요시아끼 申请人:니시무로 타이죠；가부시끼가이샤 도시바； IPC主号:
专利说明:
Semiconductor device {SEMICONDUCTOR DEVICE} [53] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a package structure in which a through hole in which a conductive member is embedded in a semiconductor chip and leads wiring from the forming surface side and the back surface side of the semiconductor element, and is particularly suitable for a high performance semiconductor device having a reinforced power supply. will be. [54] As the power supply voltage is reduced due to the miniaturization of the semiconductor integrated circuit and the semiconductor chip size is increased due to the increase in the circuit scale, the problem of voltage drop inside the semiconductor chip is presently being brought to the fore. As a countermeasure, the package of the flip-chip structure which connects a connection terminal over the whole surface of a semiconductor chip surface, and connects face-down to a multilayer wiring board is becoming mainstream. [55] 29 is a sectional view showing a schematic structure of a conventional semiconductor device as described above. In Fig. 29, reference numeral 21 denotes a semiconductor chip, reference numeral 22 denotes a formation surface of a semiconductor element, reference numeral 23 denotes a connection terminal (conductive bump) embedded in the formation surface 22 of the semiconductor element, and reference numeral 24 denotes a fine wiring. Substrate. The semiconductor chip 21 is disposed on the fine wiring board 24 by the conductive bumps 23 electrically disposed on the formation surface 22 of the semiconductor element, and electrically connected to the semiconductor elements in the semiconductor chip 21. It is mounted. The fine wiring board 24 has wiring layers (multilayer wiring: 24B) formed on both sides and inside of the insulating substrate 24A made of resin, etc., and the bumps 23 are placed on the mounting surface side of the semiconductor chip 21. The wiring layer is formed in the position corresponding to). This wiring layer is led to the rear surface side through the wiring layer portion provided in the substrate 24A and electrically connected to a connection terminal (conductive bump) 25 for connecting to the mounting substrate. [56] However, in order to realize the semiconductor device having the structure described above, many signal lines connected to the semiconductor chip 21 must be arranged in the fine wiring board 24, so that fine patterning is required and the cost is very expensive. [57] Moreover, the package of the structure which connects many connection terminals with the shortest distance is also proposed by mounting in the state which the circuit formation surface of a semiconductor chip faced and arrange | positioned in order to transmit a signal at high speed between several semiconductor chips. [58] However, in the case of such a package structure, when the power supply is to be reinforced, since the circuit formation surfaces of each semiconductor chip face each other, the power supply can only be provided from the outer peripheral portion of the chip, thereby solving the problem of voltage drop inside the semiconductor chip. Can not. [59] As described above, the problem of lowering the power supply voltage and the voltage drop inside the semiconductor chip is presently known, but there is a problem that the cost is high when the problems are solved. [60] In addition, although a semiconductor device having a package structure capable of transmitting signals at high speed has been proposed, the problem of voltage drop inside the semiconductor chip cannot be solved. [61] SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device capable of realizing required functions at a minimum cost. [62] In addition, another object of the present invention is to provide a semiconductor device capable of suppressing a voltage drop inside a semiconductor chip even if the semiconductor chip size is enlarged due to a decrease in power supply voltage due to miniaturization of a semiconductor integrated circuit or an increase in circuit scale. There is. [63] Further, another object of the present invention is to provide a semiconductor device having a high-performance, inexpensive package structure. [1] BRIEF DESCRIPTION OF THE DRAWINGS It is a figure for demonstrating the semiconductor device which concerns on 1st Embodiment of this invention, FIG. 1 (a) is sectional drawing which shows schematic structure, FIG. 1 (b) is a part of FIG. 1 (a). Enlarged section. [2] FIG. 2 is a cross-sectional view for explaining the semiconductor device according to the second embodiment of the present invention. FIG. 2A is a cross-sectional view showing a schematic configuration, and FIG. 2B is a part of FIG. 2A. Enlarged section. [3] 3 is a schematic cross-sectional view for explaining the semiconductor device according to the third embodiment of the present invention. [4] 4 is a schematic cross-sectional view for explaining the semiconductor device according to the fourth embodiment of the present invention. [5] 5 is a schematic cross-sectional view for explaining the semiconductor device according to the fifth embodiment of the present invention. [6] 6 is a schematic cross-sectional view for explaining the semiconductor device according to the sixth embodiment of the present invention. [7] 7 is a schematic cross-sectional view for explaining the semiconductor device according to the seventh embodiment of the present invention. [8] 8 is a schematic cross-sectional view illustrating a semiconductor device according to an eighth embodiment of the present invention. [9] 9 is a schematic cross-sectional view illustrating a semiconductor device according to a ninth embodiment of the present invention. [10] 10 is a schematic cross-sectional view illustrating a semiconductor device according to a tenth embodiment of the present invention. [11] 11 is a schematic cross-sectional view for explaining the semiconductor device according to the eleventh embodiment of the present invention. [12] 12 is a schematic cross-sectional view illustrating a semiconductor device according to a twelfth embodiment of the present invention. [13] Fig. 13 is a schematic cross-sectional view for explaining the semiconductor device according to the thirteenth embodiment of the present invention. [14] 14 is a schematic cross-sectional view illustrating a semiconductor device according to a fourteenth embodiment of the present invention. [15] 15 is a schematic cross-sectional view illustrating a semiconductor device according to a fifteenth embodiment of the present invention. [16] 16 is a schematic cross-sectional view for explaining the semiconductor device according to the sixteenth embodiment of the present invention. [17] 17 is a schematic cross-sectional view illustrating a semiconductor device according to a seventeenth embodiment of the present invention. [18] 18 is a schematic cross-sectional view illustrating a semiconductor device according to an eighteenth embodiment of the present invention. [19] 19 is a schematic cross-sectional view illustrating a semiconductor device according to a nineteenth embodiment of the present invention. [20] 20 is a schematic cross-sectional view illustrating a semiconductor device according to a twentieth embodiment of the present invention. [21] Fig. 21 is a schematic cross sectional view for explaining the semiconductor device according to the twenty-first embodiment of the present invention. [22] Fig. 22 is a schematic sectional view illustrating a semiconductor device according to a twenty second embodiment of the present invention. [23] Fig. 23 is a schematic cross sectional view for explaining the semiconductor device according to the twenty third embodiment of the present invention. [24] 24 is a schematic cross-sectional view illustrating a semiconductor device according to a twenty-fourth embodiment of the present invention. [25] 25 is a schematic cross-sectional view illustrating a semiconductor device according to a twenty fifth embodiment of the present invention. [26] Fig. 26 is a schematic cross sectional view for explaining the semiconductor device according to the 26th embodiment of the present invention. [27] Fig. 27 is a schematic cross sectional view for explaining a semiconductor device according to a 27th embodiment of the present invention. [28] Fig. 28 is a schematic sectional view illustrating a semiconductor device according to a twenty eighth embodiment of the present invention. [29] 29 is a schematic cross-sectional view for explaining a conventional semiconductor device. [30] <Explanation of symbols for the main parts of the drawings> [31] 1, 1-1, 1-2, 21: semiconductor chip [32] 2, 2-1, 2-2, 22: formation surface of semiconductor element [33] 3: through hole [34] 4, 4-1, 4-2, 23: first connection terminal [35] 5: second connection terminal [36] 6: bonding wire [37] 7: wiring board [38] 7A: Insulating Substrate [39] 7B: wiring layer (third connection terminal) [40] 7 ': TAB tape [41] 8: lead frame [42] 9, 9 ', 26: Package [43] 10: heat slag [44] 11: high heat radiation resin [45] 12: beam lead [46] 13: conductive bump (fourth connection terminal) [47] 14: side insulating film [48] 15: buried metal (conductive member) [49] 16: interlayer insulation film and surface protection insulation film [50] 17: In-chip wiring [51] 18: back insulation film [52] 24: fine wiring board [64] The semiconductor device according to the present invention includes a first semiconductor chip on which a semiconductor element is formed, a first connection terminal provided on the side of the semiconductor element formation surface of the first semiconductor chip, and electrically connected to the semiconductor element, 1st connection terminal embedded in the through-hole which penetrates a semiconductor chip, and the 2nd connection terminal provided in the back surface side of the formation surface of the semiconductor element in the said 1st semiconductor chip, and electrically connected to the semiconductor element via this electroconductive member. And a wiring board on which the first semiconductor chip is mounted, and at least a portion thereof is formed at a position corresponding to any one of the first connecting terminal and the second connecting terminal on the wiring board, so that the first connecting terminal or the second It is characterized by including the 3rd connection terminal electrically connected to a connection terminal. [65] Moreover, the semiconductor device which concerns on this invention is the 1st semiconductor chip in which the semiconductor element was formed, the 1st connection terminal provided in the formation surface side of the semiconductor element in the said 1st semiconductor chip, and electrically connected to this semiconductor element, A conductive member embedded in a through-hole penetrating through the first semiconductor chip, and provided on the rear surface side of the formation surface of the semiconductor element in the first semiconductor chip and electrically connected to the semiconductor element through the conductive member. A lead frame having two connection terminals and the first semiconductor chip mounted thereon, the lead frame being at a position opposite to one of the first connection terminal and the second connection terminal and electrically connected to at least a portion thereof; And a package sealing the lead portion and the first semiconductor chip. [66] The semiconductor device according to the present invention includes a first semiconductor chip having a semiconductor element formed thereon, a first connection terminal provided on the side of the semiconductor element formation surface of the first semiconductor chip, and electrically connected to the semiconductor element; A second conductive member embedded in the through-hole penetrating the first semiconductor chip, and a second surface provided on the back surface side of the formation surface of the semiconductor element in the first semiconductor chip and electrically connected to the semiconductor element through the conductive member. A connection terminal is provided, and the said 1st connection terminal or a 2nd connection terminal is connected to a mounting board, and it is mounted, It is characterized by the above-mentioned. [67] Moreover, the semiconductor device which concerns on this invention is a semiconductor chip in which the semiconductor element was formed, the some 1st connection terminal provided in the formation surface side of the semiconductor element in the said semiconductor chip, and electrically connected to this semiconductor element, and the said semiconductor A plurality of second conductive members embedded in the plurality of through holes penetrating the chip, and a plurality of second electrodes provided on the rear surface side of the formation surface of the semiconductor element in the semiconductor chip and electrically connected to the semiconductor element through the conductive member; A connection terminal is provided, and the average density which arrange | positions the said 1st connection terminal was made higher than the average density which arrange | positions the said 2nd connection terminal, It is characterized by the above-mentioned. [68] A semiconductor device according to the present invention includes a semiconductor chip on which a semiconductor element is formed, a first connection terminal provided on the side of the semiconductor element formation surface of the semiconductor chip, and electrically connected to the semiconductor element, and through the semiconductor chip. And a second connecting terminal provided on the back surface side of the formation surface of the semiconductor element in the semiconductor chip, and electrically connected to the semiconductor element via the conductive member. A part of at least one of the first connection terminal and the second connection terminal is arranged in a distributed area throughout the semiconductor chip, and a power supply potential or a ground potential is applied. [69] In the semiconductor device according to the present invention, at least part of the connection terminals of the first connection terminal or the second connection terminal in the first semiconductor chip that are not used for opposing connection with the wiring board, and the wiring. And a bonding wire for connecting the third connection terminal formed on the substrate. [70] In the semiconductor device according to the present invention, at least a part of the first connection terminal or the second connection terminal of the first semiconductor chip, which is not used for the opposing connection with the lead frame, and the lead frame. Bonding wires for connecting the inner lead portion, and a package for sealing the inner lead portion of the lead frame and the first semiconductor chip. [71] In the semiconductor device according to the present invention, the semiconductor device further comprises a second semiconductor chip stacked on the first semiconductor chip, wherein the first semiconductor terminal and the second connection terminal of the first semiconductor chip are connected to the wiring board. At least a part of the connection terminal of the side which is not used for opposing connection is connected to the said 2nd semiconductor chip, It is characterized by the above-mentioned. [72] In the semiconductor device according to the present invention, the semiconductor device further comprises second to nth (n is a positive integer of 3 or more) semiconductor chips stacked on the first semiconductor chip, and includes a first connection terminal in the first semiconductor chip. Or at least one part of the connection terminal of the side which is not used for the opposing connection with the said wiring board among the 2nd connection terminals is connected to the said 2nd-nth semiconductor chip, It is characterized by the above-mentioned. [73] A semiconductor device according to the present invention, further comprising a second semiconductor chip stacked on the first semiconductor chip, wherein the first frame or the second connection terminal of the first semiconductor chip is connected to the lead frame. At least a part of the connection terminal of the side which is not used for opposing connection is connected to the said 2nd semiconductor chip, It is characterized by the above-mentioned. [74] In the semiconductor device according to the present invention, the semiconductor device further comprises second to nth (n is a positive integer of 3 or more) semiconductor chips stacked on the first semiconductor chip, and includes a first connection terminal in the first semiconductor chip. Or at least one part of the connection terminal of the side which is not used for the opposing connection with the said lead frame among the 2nd connection terminals is connected to the said 2nd-nth semiconductor chip, It is characterized by the above-mentioned. [75] In the semiconductor device according to the present invention, the semiconductor device further comprises a second semiconductor chip stacked on the first semiconductor chip, the first connecting terminal or the second connecting terminal of the first semiconductor chip is mounted on a mounting board, Among these connection terminals, at least a part of the connection terminals that are not used for external connection with the mounting substrate are connected to the second semiconductor chip. [76] In the semiconductor device according to the present invention, the semiconductor device further comprises second to nth (n is a positive integer of 3 or more) semiconductor chips stacked on the first semiconductor chip, and includes a first connection terminal in the first semiconductor chip. Alternatively, the second connecting terminal is mounted on the mounting board, and among these connecting terminals, at least part of the connecting terminals not used for external connection with the mounting board is connected to the second to n-th semiconductor chips. It features. [77] In the semiconductor device according to the present invention, the semiconductor device further comprises a bonding wire for connecting at least part of the plurality of stacked semiconductor chips. [78] In the semiconductor device according to the present invention, the semiconductor device further comprises a conductive bump for connecting at least a portion of the plurality of stacked semiconductor chips. [79] In the semiconductor device according to the present invention, at least two adjacent semiconductor chips of the plurality of semiconductor chips are connected to face each other with the formation surfaces of the semiconductor elements. [80] Moreover, the semiconductor device which concerns on this invention is the 1st semiconductor chip in which the semiconductor element was formed, the 1st connection terminal provided in the formation surface side of the semiconductor element in the said 1st semiconductor chip, and electrically connected to this semiconductor element, A conductive member embedded in a through-hole penetrating through the first semiconductor chip, and provided on the rear surface side of the formation surface of the semiconductor element in the first semiconductor chip and electrically connected to the semiconductor element through the conductive member. 2 connection terminals, the 2nd semiconductor chip laminated | stacked on the said 1st semiconductor chip, and the 3rd connection terminal provided only in the formation surface side of the semiconductor element in the said 2nd semiconductor chip, and the 1st in the said 1st semiconductor chip Either one of a connection terminal and a 2nd connection terminal is provided in the position which opposes the 3rd connection terminal in the said 2nd semiconductor chip, and the said 1st peninsula is connected through the opposing connection terminals. The sieve chip and the 2nd semiconductor chip are electrically connected. [81] In the semiconductor device according to the present invention, the second semiconductor chip is thicker than the first semiconductor chip. [82] In the semiconductor device according to the present invention, the second semiconductor chip is larger than the first semiconductor chip. [83] The semiconductor device according to the present invention is characterized by further comprising a filling resin provided in a gap including a connection point between the first semiconductor chip and the second semiconductor chip. [84] Moreover, the semiconductor device which concerns on this invention provides the semiconductor chip in which the semiconductor element was formed, the 1st connection terminal provided in the formation surface side of the semiconductor element in the said semiconductor chip, and electrically connected to this semiconductor element, and the said semiconductor chip. A conductive member embedded in a through hole to penetrate therein, a second connecting terminal provided on the rear surface side of the formation surface of the semiconductor element in the semiconductor chip and electrically connected to the semiconductor element via the conductive member, and the semiconductor chip A third connection terminal formed on the mounted wiring board, the wiring board and partially disposed at a position facing the first connection terminal of the semiconductor chip, and electrically connected to the semiconductor chip; Bonding wires for connecting at least a portion of the second connection terminals in the second connection terminal and the third connection terminals formed on the wiring board, the bonding wires and the A sealing resin provided on the upper surface of the wiring board including the semiconductor chip, and a fourth portion provided on the rear surface side of the surface on which the semiconductor chip of the wiring board is mounted for connecting to the mounting board, and electrically connected to the third connecting terminal. And a connection terminal, wherein the first connection terminal is mainly used for applying a power supply potential and a ground potential, and the second connection terminal is mainly used for a signal system. [85] Moreover, the semiconductor device which concerns on this invention is provided with the semiconductor chip in which the semiconductor element was formed, the 1st connection terminal provided along the outer peripheral part by the side of the formation surface side of the semiconductor element in the said semiconductor chip, and electrically connected to this semiconductor element, and A conductive member embedded in each of the through-holes distributed and spread throughout the semiconductor chip, and provided on the rear surface side of the formation surface of the semiconductor element in the semiconductor chip, and electrically connected to the semiconductor element via the conductive member, respectively. A second connection terminal, a wiring board on which the semiconductor chip is mounted, a third connection terminal formed at a position opposite to the second connection terminal in the semiconductor chip, and electrically connected to the semiconductor chip, Bonding wires for connecting at least a portion of first connection terminals with a third connection terminal formed on the wiring board, the bonding wires and the In order to connect with the sealing resin provided in the upper surface of the wiring board containing a conductor chip, and the mounting board | substrate, it is provided in the back surface side of the surface where the said semiconductor chip of the said wiring board is mounted, and is electrically connected with the said 3rd connection terminal. And a fourth connection terminal, wherein the second connection terminal is mainly used for applying a power supply potential and a ground potential, and the first connection terminal is mainly used for a signal system. [86] According to the present invention, the following effects can be obtained. [87] That is, according to the structure of this invention, the arrangement | positioning position of a connection terminal can be increased and it is possible to increase the number of connection terminals, without increasing a connection density. [88] According to the structure of this invention, since a semiconductor chip is mounted in a lead frame, it is possible to provide a semiconductor device more inexpensive than when using the wiring board of this invention. [89] According to the structure of this invention, CSP which increased the number of connection terminals can be implement | achieved, without increasing connection density, and mounting efficiency can be improved significantly. [90] According to the structure of this invention, the increase of the chip size by the through hole formed in a semiconductor chip can be suppressed. [91] According to the structure of this invention, since a connection terminal is disperse | distributed and arrange | positioned throughout the surface of a semiconductor chip, the voltage drop in a semiconductor chip can be reduced without increasing a connection density. [92] According to the configuration of the present invention, the number of connection terminals can be increased without using an expensive fine wiring board, and the necessary functions can be realized at minimum cost. [93] According to the structure of this invention, since a semiconductor chip is mounted in the lead frame which is cheaper than a wiring board, it can implement | achieve a semiconductor device more inexpensive than the above-mentioned semiconductor device. [94] According to the configuration of the present invention, the number of connection terminals can be increased without using an expensive fine wiring board, and signal transmission between a plurality of semiconductor chips can be carried out at the shortest distance, thereby achieving high performance of the semiconductor device. . [95] According to the structure of this invention, in addition to the effect of the semiconductor device of this invention, it becomes possible to form many connection point between a some semiconductor chip. [96] According to the structure of this invention, since the thin 1st semiconductor chip provided with the through hole can be reinforced by a 2nd semiconductor chip, the risk which a 1st semiconductor chip is damaged can be reduced significantly. [97] According to the structure of this invention, it is possible to increase the number of connection terminals, without using an expensive fine wiring board, and can also reduce the voltage drop in a semiconductor chip. [98] <Embodiment of the invention> [99] The gist of the present invention is to mount a semiconductor chip provided with a through hole in which a conductive member is embedded in various forms, and only a small number is required, but the wiring of a power supply system or a grounding system that needs to be dispersed throughout the surface of the semiconductor chip. Although it is not necessary to disperse | distribute connection or the whole area | region over the surface of a semiconductor chip, the wiring of many required signal systems is rearranged on both surfaces of a semiconductor chip by drawing to the back side of a semiconductor chip through the conductive member embedded in the through hole. [100] And when mounting a semiconductor chip by face-up, a through hole is allocated to a power supply system and a grounding system, and a power supply is reinforced directly from the back surface of the formation surface of a semiconductor element. On the other hand, a signal line requiring fine connection is derived by wire bonding from a pad provided on the outer peripheral portion of the formation surface of the semiconductor element. This combination makes it possible to realize a high performance semiconductor device in which a power supply is reinforced without using an expensive fine wiring board. [101] On the other hand, in the case where the semiconductor chip is mounted face down, a flip chip connection is performed by two-dimensionally arranging a power pad or a ground pad on the formation surface of the semiconductor element. The signal line requiring fine connection is led out to the rear surface of the formation surface of the semiconductor element through the through hole formed in the outer peripheral portion of the semiconductor element, and drawn out from the rear surface side by wire bonding. In the case of this combination as well, a high-performance semiconductor device in which a power supply is reinforced without using an expensive fine wiring board can be realized. [102] Moreover, as a power generation example, it becomes possible to laminate | stack another semiconductor chip on the semiconductor chip of said two examples. In particular, when the connection density between two semiconductor chips is high, the following semiconductor chips can be faced up to realize multi-terminal connection without going through an expensive wiring board. [103] DESCRIPTION OF EMBODIMENTS Various embodiments of the present invention will be described below with reference to the drawings. [104] [First Embodiment] [105] 1 (a) and 1 (b) are each for explaining the semiconductor device according to the first embodiment of the present invention, and FIG. 1 (a) is a schematic cross-sectional view and FIG. 1 (b). Is a partially enlarged cross-sectional view of FIG. As shown in FIG. 1A, the semiconductor chip 1 is mounted with the formation surface 2 of the semiconductor element (internal circuit) facing the wiring board 7 (face down). On the formation surface 2 of the semiconductor element, connection terminals (conductive bumps 4) are dispersed and formed (for example, array type) throughout, and the wiring layer of the wiring board 7 is formed through the connection terminals 4. 7B) is electrically connected. The wiring board 7 has wiring layers (multilayer wiring: 7B) formed on both sides and inside of the insulating substrate 7A including resin, respectively, and the bumps 4 are placed on the mounting surface side of the semiconductor chip 1. The wiring layer is disposed at a position corresponding to the wiring layer. The wiring layer 7B is led to the rear surface side through the wiring layer portion provided in the substrate 7A and electrically connected to a connection terminal (conductive bump) 13 for connecting to the mounting substrate. [106] In addition, a through hole 3 in which the conductive member is embedded is formed in the outer peripheral portion of the semiconductor chip 1, and a connection terminal (pad) 5 is formed on the back surface of the chip of the conductive member embedded in the through hole 3. Each is formed. The connection terminal 5 and the wiring board 7 are connected by a bonding wire 6. The semiconductor chip 1 and the bonding wire 6 on the wiring board 7 are sealed with a package 9 made of resin, ceramic, or the like. [107] In the above configuration, the vicinity of the through hole 3 is as shown in Fig. 1B. An insulating film 14 is formed on the sidewall of the through hole 3 formed in the semiconductor chip 1, and the buried metal (conductive member 15) is formed in the through hole 3 in an insulated state from the chip 1. It is installed. On the side of the formation surface 2 of the semiconductor element in the chip 1, for example, an in-chip wiring 17 including copper, aluminum, etc., and one end electrically connected to the conductive member 15 is provided. have. The other end of the in-chip wiring 17 is electrically connected to a semiconductor element (internal circuit). The entire surface of the semiconductor element formation surface 2 of the chip 1 including the in-chip wiring 17 is covered with an interlayer insulating film and a surface protective film 16. On the other hand, a bonding pad (connection terminal 5) is provided on the conductive member 15 on the back side of the element formation surface of the chip 1, and one end of the bonding wire 6 is attached to the bonding pad 5. It is ball bonded. In addition, a back insulating film 18 is formed on the back surface of the chip 1 except for the vicinity of the through hole 3. [108] The greatest advantage of this structure is that in the conventional plastic BGA package, all of the connectable regions, i.e., the entire area of the surface facing the wiring board 7 of the semiconductor chip 1 and the outer peripheral portion of the rear surface thereof, are connected to the connection terminals 4 and 5. By being able to disperse | distribute, it becomes possible to increase the number of connection points, without increasing actual connection density. [109] In addition, by allocating the connection terminals 4 distributed on the formation surface 2 of the semiconductor element to the power supply system and the ground system, the convenience of the present structure can be utilized to the maximum. In general, it is important to disperse the connection terminals of the power supply system and the ground system on the entire surface of the semiconductor chip 1, and a plurality of connection points are not necessarily required. On the other hand, the connection of the signal system naturally requires a large number of connection points, but on the other hand, it is not always necessary to be distributed over the entire surface of the semiconductor chip 1. Therefore, the number of terminals is small and the connection terminal 4 arrange | positioned can be arrange | positioned using the cheap wiring board 7. Moreover, since many signal terminals are arrange | positioned in the state extended further by the bonding wire 6 from the outer peripheral part of a chip, it becomes possible to arrange | position sufficiently with the cheap wiring board 7 here, too. [110] Therefore, according to the semiconductor device according to the first embodiment, necessary functions can be realized at minimum cost. In addition, even if the semiconductor chip size is enlarged due to a decrease in the power supply voltage due to the miniaturization of the semiconductor integrated circuit or an increase in the circuit scale, the voltage drop inside the semiconductor chip can be suppressed. In addition, a semiconductor device having a high performance and inexpensive package structure can be obtained. [111] Second Embodiment [112] 2 (a) and 2 (b) are for explaining the semiconductor device according to the second embodiment of the present invention, respectively, FIG. 2 (a) is a schematic sectional view, and FIG. 2 (b) Is a partially enlarged cross-sectional view of FIG. In the second embodiment, the semiconductor chip 1 is mounted with the back surface of the formation surface 2 of the semiconductor element facing the wiring board 7 (face up). The through hole 3 in which the conductive member 15 is embedded is distributedly disposed throughout the semiconductor chip 1, and a connection terminal (conductive bump: 5) formed on the back surface of the chip 1 through the through hole 3. The wiring board 7 is connected to the wiring board 7 by using. In addition, a connection terminal (pad) 4 similar to a general semiconductor device is formed on the outer circumferential portion of the formation surface 2 of the semiconductor element 1 of the semiconductor chip 1, and a wiring board (wire wiring) is formed from the connection terminal 4 by wire bonding. It is electrically connected with the wiring layer 7B of 7). [113] In the configuration as described above, the vicinity of the through hole 3 is as shown in Fig. 2B. An insulating film 14 is formed on the sidewall of the through hole 3 formed in the semiconductor chip 1, and the conductive member 15 is embedded in the through hole 3 in an insulated state from the chip 1. . On the side of the surface of the semiconductor element formation surface 2 of the chip 1, an in-chip wiring 17 having one end electrically connected to the conductive member 15 is provided, and the other end of the in-chip wiring 17 is a semiconductor. It is electrically connected to an element (internal circuit). The whole surface of the formation surface 2 of the semiconductor element of the chip 1 including the in-chip wiring 17 is covered with an interlayer insulating film and a surface protection film 16, and conductive bumps (connections) are connected to the conductive member 15 on the rear surface side. Terminal: 5) is installed. The wiring layer 7B of the wiring board 7 is connected to this bump 5. The back surface of the chip 1 except for the vicinity of the through hole 3 is covered with a back surface insulating film 18. [114] This structure also has the feature that the connection terminals 4 and 5 are dispersed in positions suitable for connection, as in the above-described first embodiment, so that the number of connection points can be increased without increasing the actual connection density. . In addition, in the case of this structure, it is preferable to arrange | position the power supply system and the grounding system to the bump 5 for the same reason as the said 1st Embodiment. [115] [Third and fourth embodiment] [116] 3 and 4 are schematic cross-sectional views for explaining the semiconductor devices according to the third and fourth embodiments of the present invention, respectively, and are modifications of the semiconductor devices according to the first and second embodiments described above. In these 3rd and 4th embodiment, the lead frame 8 of low cost is used instead of the wiring board 7. As shown in FIG. Since the other basic structure is the same as that of 1st and 2nd embodiment, in FIG. 3 and FIG. 4, the same code | symbol is attached | subjected to the same component part as FIG. 1 and FIG. 2, and the detailed description is abbreviate | omitted. [117] In general, when the semiconductor chip 1 is mounted on the lead frame 8, the same power supply and ground plane as in the case of using the wiring board 7 cannot be formed. However, in the semiconductor device according to the present embodiment, since both the power supply and the ground are directly supplied from directly under the semiconductor chip 1, substantially sufficient performance can be ensured. [118] [5th, 6th Embodiment] [119] 5 and 6 are schematic cross-sectional views for explaining the semiconductor devices according to the fifth and sixth embodiments of the present invention, respectively, and are other modifications of the semiconductor devices according to the first and second embodiments described above. In these fifth and sixth embodiments, the semiconductor chip 1 and the wiring board 7 are mounted on a heat slag 10. The heat slag 10 is a ceramic plate or a metal plate on which a metal layer or metal wiring is formed, and the metal part is connected to a power source or a ground. [120] In the fifth embodiment, the semiconductor chip 1 is mounted on the heat slag 10 with the formation surface 2 of the semiconductor element facing downward. A connection terminal (conductive bump) 4 provided on the formation surface 2 of the semiconductor element 1 of the semiconductor chip 1 is connected to a metal portion on the heat slag 10. In addition, the wiring board 7 is disposed to surround the semiconductor chip 1. The mounting connecting terminal 13 is provided on the upper surface of the wiring board 7. The connection terminal (pad) 5 of the semiconductor chip 1 and the wiring 7B of the wiring board 7 are electrically connected by the bonding wires 6. The region near the chip 1 of the semiconductor chip 1, the bonding wire 6, and the wiring board 7 is sealed with a package 9 containing resin or the like. [121] In the above-described configuration, the connection terminals 4 distributed on the formation surface 2 of the semiconductor element are assigned to the power supply system and the ground system, and the element formation surface 2 side of the semiconductor chip 1 is provided. Is connected to the metal wiring layer on the heat slag 10 through the connection terminal 4 from the. Moreover, the connection terminal 5 arrange | positioned along the outer periphery of the chip | tip of the back surface side of the formation surface 2 of a semiconductor element is allocated to the signal system, and the through-hole (from the element formation surface 2 side of the semiconductor chip 1) 3 is connected to the said connection terminal 13 via the wiring 7B among the electroconductive member 15, the connection terminal 5, the bonding wire 6, and the wiring board 7 inside. [122] On the other hand, in the sixth embodiment, the semiconductor chip 1 is mounted on the heat slag 10 with the formation surface 2 of the semiconductor element facing up. A connection terminal (conductive bump) 5 provided through the through hole 3 on the back surface side of the semiconductor chip 1 is connected to the metal wiring layer on the heat slag 10. In addition, the wiring board 7 is disposed so as to surround the semiconductor chip 1, and the mounting connection terminal 13 for mounting is provided on the upper surface of the wiring board 7. The connecting terminal (pad) 4 provided on the side of the semiconductor element formation surface 2 of the semiconductor chip 1 and the wiring 7B of the wiring board 7 are electrically connected by the bonding wires 6. do. The area | region near the chip 1 of the said semiconductor chip 1, the bonding wire 6, and the said wiring board 7 is sealed by the package 9 containing resin etc. [123] In the above-described configuration, the connection terminals 5 distributed on the rear surface side of the formation surface 2 of the semiconductor element are assigned to the power supply system and the grounding system, and the element formation surface of the semiconductor chip 1 ( It is connected to the metal wiring layer on the said heat slag 10 via the connection terminal 5 from 2) side. Moreover, the connection terminal 4 arrange | positioned along the outer periphery of the chip | tip of the formation surface 2 side of a semiconductor element is allocated to the signal system, and in this connection terminal 4, the bonding wire 6, and the wiring board 7, It is connected to the said connection terminal 13 via the wiring 7B, respectively. [124] [7th, 8th Embodiment] [125] 7 and 8 are schematic cross-sectional views for explaining the semiconductor device according to the seventh and eighth embodiments of the present invention, respectively, and are modifications of the semiconductor device according to the fifth and sixth embodiments described above. In these seventh and eighth embodiments, the high heat dissipation resin layer 11 is interposed between the heat slag 10 and the semiconductor chip 1 in FIGS. 5 and 6. [126] At this time, in the seventh embodiment, the connecting terminal 4 provided on the formation surface 2 of the semiconductor element of the semiconductor chip 1 is connected to the metal portion on the heat slag 10, and the semiconductor chip 1 ) And the heat slag 10 are filled with the high heat dissipation resin layer 11. [127] On the other hand, in the eighth embodiment, the connecting terminal 5 provided through the through hole 3 on the rear surface side of the semiconductor chip 1 is connected to the metal portion on the heat slag 10, and the semiconductor chip 1 ) And the heat slag 10 are filled with the high heat dissipation resin layer 11. [128] According to such a structure, heat dissipation can be improved more compared with the semiconductor device which concerns on 5th and 6th embodiment. [129] 7 and 8 illustrate the case where the semiconductor chip 1 and the heat slag 10 are individually connected using the connection terminals 4 and 5 as an example, the connection terminals 4 and 5 will be described. When using as a power supply system or a grounding system, you may connect collectively by using the resin with high electroconductivity to the high heat radiation resin layer 11. [130] [Ninth, tenth embodiment] [131] 9 and 10 are schematic cross-sectional views for explaining the semiconductor device according to the ninth and tenth embodiments of the present invention, respectively, and are modifications of the semiconductor device according to the seventh and eighth embodiments described above. In these ninth and tenth embodiments, the TAB technique is used in place of the wire bonding technique. [132] That is, in the ninth embodiment, the semiconductor chip 1 is mounted on the heat slag 10 with the formation surface 2 of the semiconductor element facing downward. The connection terminal 4 provided in the formation surface 2 of the semiconductor element of the semiconductor chip 1 is connected to the metal wiring layer on the heat slag 10. The high heat radiation resin layer 11 is filled in the gap between the element formation surface 2 of the semiconductor chip 1 and the heat slag 10. In addition, the semiconductor chip 1 is disposed in the device hole of the TAB tape 7 'and is fixed on the heat slag 10A provided to surround the semiconductor chip 1. The mounting connection terminal 13 is provided in the lead formed in the upper surface of this TAB tape 7 '. The beam lead 12 provided on the TAB tape 7 'is connected to the connection terminal 5 of the semiconductor chip 1. The area | region near the chip 1 of the said semiconductor chip 1, the beam lead 12, and the said TAB tape 7 'is sealed by the package 9' formed by dropping potting resin, for example. [133] In the above-described configuration, the connection terminals 4 distributed on the formation surface 2 of the semiconductor element are assigned to a power supply system or a ground system, and the element formation surface 2 side of the semiconductor chip 1 is provided. Is connected to the metal part on the heat slag 10 via the connection terminal 4 from the. In addition, the connection terminal 5 on the back surface side of the formation surface 2 of the semiconductor element is assigned to the signal system, and the conductive member 15 in the through hole 3 from the element formation surface 2 side of the semiconductor chip 1. The connecting terminal 13 is connected to the connecting terminal 13 via a wiring 7B of the connecting terminal 5, the beam lead 12, and the wiring board 7, respectively. [134] On the other hand, in the tenth embodiment, the semiconductor chip 1 is mounted on the heat slag 10 with the formation surface 2 of the semiconductor element facing up. The connection terminal 5 provided through the through hole 3 on the back surface side of the semiconductor chip 1 is connected to the metal wiring layer on the heat slag 10. The high heat dissipation resin layer 11 is filled in the gap between the back surface of the semiconductor chip 1 and the heat slag 10. In addition, the semiconductor chip 1 is disposed in the device hole of the TAB tape 7 'and is fixed on the heat slag 10A provided to surround the semiconductor chip 1. The mounting connecting terminal 13 is provided on the lead of the upper surface of the TAB tape 7 '. The beam lead of the TAB tape 7 'is connected to the connection terminal 4 provided on the side of the formation surface 2 of the semiconductor element in the semiconductor chip 1. The area | region near the chip 1 of the said semiconductor chip 1, the beam lead 12, and the said TAB tape 7 'is sealed by the package 9' formed by dropping potting resin, for example. [135] In the configuration as described above, the connection terminals 5 distributed on the rear surface of the formation surface 2 of the semiconductor element are assigned to a power supply system or a grounding system, and the element formation surface 2 of the semiconductor chip 1 is provided. Is connected to the metal wiring layer on the heat slag 10 via the connecting terminal 5 from the side. In addition, the connecting terminal 4 on the side of the formation surface 2 of the semiconductor element is assigned to a signal system, and through the wiring 7B of the connecting terminal 4, the beam lead 12, and the wiring board 7, respectively. It is connected to the said connection terminal 13. [136] According to the ninth and tenth embodiments, the present invention can be applied to a semiconductor device using TAB technology while improving heat dissipation as compared with the semiconductor devices according to the fifth and sixth embodiments. [137] In addition, even if the resin layer 11 is an insulating heat insulating material, since the heat slag 10 is connected by the connecting terminals 4 and 5, compared with the case where simply bonding with heat insulating resin, high heat dissipation can be obtained. . [138] In addition, in FIG. 9 and FIG. 10, the case where the semiconductor chip 1 and the heat slag 10 are individually connected using the connection terminal 4 and 5 was demonstrated as an example, However, with the 7th and 8th embodiment, FIG. Similarly, when high conductivity resin is used for the high heat dissipation resin layer 11, you may connect collectively. [139] [11th and 12th embodiment] [140] 11 and 12 are schematic cross-sectional views for explaining the semiconductor device according to the eleventh and twelfth embodiments of the present invention, respectively, and are modifications of the semiconductor device according to the first and second embodiments described above. In these eleventh and twelfth embodiments, a heat sink is provided on the semiconductor chip 1 of the package 9. Here, the heat slag 10 is used as a heat sink, and the surface of this heat slag 10 is exposed without resin coating. [141] In addition, in this embodiment, since the heat slag 10 is used only for heat dissipation, it is not necessary to apply a potential. Therefore, it does not necessarily need to be a conductor, and it does not matter even if it is a simple ceramic which does not have wiring. Of course, metal may be sufficient. [142] According to the configuration as described above, the heat dissipation effect can be further enhanced, and thus it is suitable for using the semiconductor chip 1 having a large amount of heat generation. [143] [Thirteenth and Fourteenth Embodiments] [144] 13 and 14 are schematic cross-sectional views for explaining the semiconductor device according to the thirteenth and fourteenth embodiments of the present invention, respectively, and are modifications of the semiconductor device according to the third and fourth embodiments described above. In these thirteenth and fourteenth embodiments, a heat sink is provided on the semiconductor chip 1 of the package 9 as in the eleventh and twelfth embodiments. Here, the heat slag 10 is provided as a heat sink, and the surface of this heat slag 10 is exposed without resin coating. [145] In addition, in this embodiment, since the heat slag 10 is used only for heat dissipation, it is not necessary to apply a potential. Therefore, it does not necessarily need to be a conductor, and it does not matter even if it is a simple ceramic which does not have wiring. Of course, metal may be sufficient. [146] According to the configuration as described above, the heat dissipation effect can be further enhanced, which is suitable for mounting the semiconductor chip 1 having a large amount of heat generation on the lead frame 8. [147] [15th to 18th Embodiments] [148] 15-18 is schematic sectional drawing which shows 15th-18th embodiment of this invention, respectively, and is an example of the development of 1st and 2nd embodiment mentioned above. In the fifteenth and seventeenth embodiments, another semiconductor chip 1-2 is laminated on the semiconductor chip 1-1 in the first embodiment, and the sixteenth and eighteenth embodiments are provided in the second embodiment. Another semiconductor chip 1-2 is laminated on the semiconductor chip 1-1. The fifteenth and sixteenth embodiments exemplify the use of the bonding wire 6 for the connection from the semiconductor chip 1-2 mounted above, and the seventeenth and eighteenth embodiments provide the semiconductor chip 1-2 mounted upward. Is an example in which the conductive bumps 4-2 are used for the connection from the (). [149] In the above-described fifteenth to eighteenth embodiments, the semiconductor chip 1-1 mounted downward in any of the embodiments includes the connection terminals 4-1 and 5 dispersedly arranged throughout the chip. By arranging a device which is sensitive to a voltage drop inside the chip, mounted downward, the performance as a semiconductor device can be improved. [150] Incidentally, in the case of the seventeenth and eighteenth embodiments, the power source potential or the ground potential can be supplied to the chip 1-2 through the chip 1-1 (through the through hole 3). Thus, a higher performance semiconductor device can be realized. [151] In these fifteenth to eighteenth embodiments, an example is shown in which all of the semiconductor chips 1-1 and 1-2 are connected between the semiconductor chips 1-1 and 1-2 and the wiring board 7. Of course, it does not matter if all combinations are not connected. In addition, the number of the semiconductor chips to be laminated is not limited to two shown in the present embodiment, and may be three or more. In the present embodiment, the semiconductor chips 1-2 stacked up are described with a conventional semiconductor chip having no through hole 3 as an example, but a semiconductor chip having a through hole 3 with a conductive member embedded therein is described. Of course, you may laminate | stack. [152] [19th, 20th embodiment] [153] 19 and 20 are schematic cross-sectional views showing semiconductor devices according to the nineteenth and twentieth embodiments of the present invention, respectively. In these nineteenth and twentieth embodiments, in order to improve heat dissipation of the semiconductor devices according to the fifteenth and sixteenth embodiments, a heat sink is provided on the semiconductor chip 1-2 of the package 9. Here, the heat slag 10 is provided as a heat sink, and the surface of this heat slag 10 is exposed without resin coating. In this structure, it is not necessary to apply a potential to the metal or metal wiring of the heat slag 10. [154] According to such a structure, heat dissipation effect can be improved more and the heat generation amount which increased by stacking the semiconductor chips 1-1, 1-2 can be reduced effectively. [155] In the nineteenth and twentieth embodiments, the heat slag 10 is provided as an example in order to improve heat dissipation of the semiconductor devices according to the fifteenth and sixteenth embodiments. Of course, it is also applicable to the seventeenth and eighteenth embodiments shown in FIG. [156] [21st and 22nd Embodiment] [157] 21 and 22 are schematic cross-sectional views showing semiconductor devices according to the twenty-first and twenty-second embodiments of the present invention, respectively. In these twenty-first and twenty-second embodiments, the semiconductor chip 1-2 is exposed on the upper surface of the package 9 in order to improve heat dissipation of the semiconductor devices according to the seventeenth and eighteenth embodiments. [158] Even in such a configuration, the heat dissipation effect can be enhanced, and the increased heat generation amount can be effectively reduced by stacking the semiconductor chips 1-1 and 1-2. [159] [23rd, 24th Embodiment] [160] 23 and 24 are schematic cross-sectional views showing semiconductor devices according to the twenty-third and twenty-fourth embodiments of the present invention, respectively. In this embodiment, the two semiconductor chips 1-1, 1-2 are opposed to each other via the conductive bumps 4-2, 5 or the conductive bumps 4-1. The gaps between the semiconductor chips 1-1 and 1-2 are reinforced by resin filling. [161] The semiconductor chip 1-1 having the through holes 3 inevitably becomes thin due to the limitation of the depth of the through holes 3. Therefore, in order to reinforce the lack of strength of the semiconductor chip 1-1 having the through hole 3, it is more preferable to design a thick and large semiconductor chip 1-2 having no opposing through hole. [162] In addition, in this embodiment, the connection terminal formed in the semiconductor chip 1-2 in the semiconductor chip 1-1 and the back surface side of the laminated surface (in the case of FIG. 23, reference numerals 4-1 and 24) By using reference numeral 5) as an external connection terminal with a mounting board, it is set as CSP (Chip Scale Package). However, you may connect these connection terminals to the package wiring board or lead frame, and form a package or a module. [163] [25th and 26th Embodiments] [164] 25 and 26 are schematic cross-sectional views showing semiconductor devices according to the twenty fifth and twenty sixth embodiments of the present invention, respectively. In these embodiments, the semiconductor devices according to the twenty-third and twenty-fourth embodiments shown in FIG. 23 and FIG. 24 are mounted on the wiring board 7, respectively, and between the semiconductor chips 1-1 and 1-2. The sealing resin is injected and packaged or modularized between the semiconductor chip 1 and the wiring board 7. In FIG.25 and FIG.26, the same code | symbol is attached | subjected to the same structural part as FIG.23 and FIG.24, and the detailed description is abbreviate | omitted. [165] According to such a structure, even if both of the semiconductor chips 1-1 and 1-2 are peeled, there is no problem of a lack of strength, and usability can also be improved. [166] In addition, in the twenty-third and twenty-fourth embodiments, the connection terminal formed on the back surface side of the laminated surface with the semiconductor chip 1-2 in the semiconductor chip 1-1 (in the case of FIG. 23, reference numeral 4-1). In the case of FIG. 24, when the number of reference numerals 5) increases and becomes high, it becomes difficult to arrange | position as a mounting board, but in this embodiment, the pitch of the external connection terminal 13 using the wiring board 7 is used. Since it can be alleviated, it is effective when it has many external connection terminals. [167] [27th and 28th Embodiment] [168] 27 and 28 are schematic cross-sectional views showing semiconductor devices according to the twenty-seventh and twenty-eighth embodiments of the present invention, respectively. In these embodiments, the heat slag 10 is used as the heat dissipation resin 11 for the semiconductor chips 1-2 in the semiconductor devices according to the 25th and 26th embodiments shown in FIGS. 25 and 26. It is glued. [169] According to this structure, the heat dissipation can be improved and the chip 1-2 can be protected by avoiding the exposure of the semiconductor chip 1-2. [170] As mentioned above, although this invention was demonstrated using 1st-28th embodiment, this invention is not limited to each said embodiment, It can be variously deformed in the range which does not deviate from the summary at the implementation stage. . In addition, each of the above-described embodiments includes inventions of various stages, and various inventions can be extracted by an appropriate combination of a plurality of constituent requirements disclosed. For example, even if some of the configuration requirements are deleted from all the configuration requirements shown in each embodiment, at least one of the problems stated in the column of the problem to be solved by the invention can be solved, and it is stated in the column of the effect of the invention. If at least one of the effects is obtained, a configuration in which this configuration requirement is omitted can be extracted as an invention. [171] As described above, according to the present invention, a semiconductor device capable of realizing necessary functions at a minimum cost is obtained. [172] In addition, a semiconductor device capable of suppressing a voltage drop inside a semiconductor chip can be obtained even if the size of the semiconductor chip is increased due to a decrease in power supply voltage or an increase in circuit scale due to miniaturization of a semiconductor integrated circuit. [173] In addition, a semiconductor device having a high performance and inexpensive package structure is obtained.
权利要求:
Claims (16) [1" claim-type="Currently amended] A first semiconductor chip having a semiconductor element formed thereon; A first connection terminal provided on the forming surface side of the semiconductor element in the first semiconductor chip and electrically connected to the semiconductor element; A conductive member embedded in a through hole penetrating the first semiconductor chip; A second connection terminal provided on the back surface side of the formation surface of the semiconductor element in the first semiconductor chip and electrically connected to the semiconductor element via the conductive member; A wiring board on which the first semiconductor chip is mounted; At least a part of the third connection terminal formed at a position corresponding to either one of the first connection terminal and the second connection terminal on the wiring board and electrically connected to the first connection terminal or the second connection terminal. A semiconductor device comprising a. [2" claim-type="Currently amended] A first semiconductor chip having a semiconductor element formed thereon; A first connection terminal provided on the forming surface side of the semiconductor element in the first semiconductor chip and electrically connected to the semiconductor element; A conductive member embedded in a through hole penetrating the first semiconductor chip; A second connection terminal provided on the back surface side of the formation surface of the semiconductor element in the first semiconductor chip and electrically connected to the semiconductor element via the conductive member; A lead frame in which the first semiconductor chip is mounted and positioned at one of the first connection terminals and the second connection terminals, the at least part of which is electrically connected; A package that seals an inner lead portion of the lead frame and the first semiconductor chip A semiconductor device comprising a. [3" claim-type="Currently amended] A first semiconductor chip having a semiconductor element formed thereon; A plurality of first connection terminals provided on the formation surface side of the semiconductor element in the first semiconductor chip and electrically connected to the semiconductor element; A plurality of conductive members embedded in the through holes penetrating the first semiconductor chip; A plurality of second connection terminals provided on the back surface side of the formation surface of the semiconductor element in the first semiconductor chip and electrically connected to the semiconductor element via the conductive member. Including, Connecting the first connection terminal and the second connection terminal to a mounting substrate A semiconductor device, characterized in that. [4" claim-type="Currently amended] The method of claim 3, At least one of the plurality of first connecting terminals and the second connecting terminal is faced to the chip side surface of the wiring board, and the average density of the one connecting terminal is made lower than the average density of the other connecting terminal. A semiconductor device, characterized in that. [5" claim-type="Currently amended] The method of claim 4, wherein A semiconductor device characterized by distributing at least one portion of at least one of the first connection terminal and the second connection terminal in the whole area of the semiconductor chip, and applying a power supply potential or a ground potential. [6" claim-type="Currently amended] The method of claim 1, At least a part of the connection terminal of the side which was not used for the opposing connection with the said wiring board among the said 1st connection terminal or the 2nd connection terminal in a said 1st semiconductor chip, and the said 3rd connection terminal formed on the said wiring board. The semiconductor device further comprises a bonding wire for connecting. [7" claim-type="Currently amended] The method of claim 2, Bonding wires connecting at least a portion of the connection terminals of the first connection terminal or the second connection terminal in the first semiconductor chip which are not used for opposing connection with the lead frame and the inner lead portion of the lead frame are further included. A semiconductor device comprising a. [8" claim-type="Currently amended] The method of claim 1, The second semiconductor chip laminated on the said 1st semiconductor chip is further included, The connection of the side which is not used for the opposing connection with the said wiring board among the 1st connection terminal or the 2nd connection terminal in the said 1st semiconductor chip. At least a portion of the terminal is connected to the second semiconductor chip. [9" claim-type="Currently amended] The method of claim 1, The semiconductor device further includes second to nth (n is a positive integer of 3 or more) semiconductor chips stacked on the first semiconductor chip, wherein the wiring is the first connection terminal or the second connection terminal of the first semiconductor chip. At least a part of the connection terminal of the side which is not used for the opposing connection with a board | substrate is connected to the said 2nd-nth semiconductor chip, The semiconductor device characterized by the above-mentioned. [10" claim-type="Currently amended] The method of claim 2, A second semiconductor chip stacked on the first semiconductor chip, wherein the first connection terminal or the second connection terminal of the first semiconductor chip is not connected to the lead frame; At least a portion of the terminal is connected to the second semiconductor chip. [11" claim-type="Currently amended] The method of claim 2, And second to nth (n is a positive integer of 3 or more) semiconductor chips stacked on the first semiconductor chip, wherein the lead is selected from the first connection terminal or the second connection terminal in the first semiconductor chip. A semiconductor device characterized by connecting at least a part of the connection terminal of the side which is not used for the opposing connection with a frame to the said 2nd-nth semiconductor chip. [12" claim-type="Currently amended] The method of claim 3, And a second semiconductor chip stacked on the first semiconductor chip, wherein the first semiconductor terminal or the second connection terminal of the first semiconductor chip is connected to the stack surface side of the first semiconductor chip and the second semiconductor chip. At least a portion of the terminal is connected to the second semiconductor chip. [13" claim-type="Currently amended] The method of claim 3, Further comprising a second to nth (n is a positive integer of 3 or more) semiconductor chip stacked on the first semiconductor chip, the first of the first connection terminal and the second connection terminal of the first semiconductor chip, A semiconductor device, wherein at least a part of the connection terminals on the side of the laminated surface of the semiconductor chip and the second semiconductor chip are connected to the second to nth semiconductor chips. [14" claim-type="Currently amended] The method according to any one of claims 8 to 13, And a bonding wire for connecting at least a portion of the plurality of stacked semiconductor chips. [15" claim-type="Currently amended] The method according to any one of claims 8 to 13, And a conductive bump for connecting at least a portion of the plurality of stacked semiconductor chips. [16" claim-type="Currently amended] A first semiconductor chip having a semiconductor element formed thereon; A first connection terminal provided on the forming surface side of the semiconductor element in the first semiconductor chip and electrically connected to the semiconductor element; A conductive member embedded in a through hole penetrating the first semiconductor chip; A second connection terminal provided on the back surface side of the formation surface of the semiconductor element in the first semiconductor chip and electrically connected to the semiconductor element via the conductive member; A second semiconductor chip stacked on the first semiconductor chip, Third connection terminal provided on the formation surface side of the semiconductor element in the second semiconductor chip Including, One of the first connection terminal and the second connection terminal in the first semiconductor chip is provided at a position facing the third connection terminal in the second semiconductor chip, and the first connection terminal is connected to each other through the opposite connection terminals. Electrically connects the semiconductor chip and the second semiconductor chip, and the second semiconductor chip is thicker or larger than the first semiconductor chip. A semiconductor device, characterized in that.
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同族专利:
公开号 | 公开日 TW518742B|2003-01-21| CN1197153C|2005-04-13| KR100574727B1|2006-04-28| US20020041027A1|2002-04-11| CN1359154A|2002-07-17| JP3854054B2|2006-12-06| JP2002118198A|2002-04-19|
引用文献:
公开号 | 申请日 | 公开日 | 申请人 | 专利标题
法律状态:
2000-10-10|Priority to JP2000309764A 2000-10-10|Priority to JPJP-P-2000-00309764 2001-10-09|Application filed by 니시무로 타이죠, 가부시끼가이샤 도시바 2002-04-17|Publication of KR20020028812A 2006-04-28|Application granted 2006-04-28|Publication of KR100574727B1
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申请号 | 申请日 | 专利标题 JP2000309764A|JP3854054B2|2000-10-10|2000-10-10|Semiconductor device| JPJP-P-2000-00309764|2000-10-10| 相关专利
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